CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI

@article{Jiang2018CMOSCompatibleDI,
  title={CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI},
  author={Junkai Jiang and Jae Hwan Chu and Kaustav Banerjee},
  journal={2018 IEEE International Electron Devices Meeting (IEDM)},
  year={2018},
  pages={34.5.1-34.5.4}
}
Cu interconnects suffer from steep rise in resistivity and severe reliability degradation for sub-20 nm line widths. Other metals, including Co and Ru, have been demonstrated with higher electromigration (EM) resistance, but exhibit lower electrical conductivity that degrades circuit performance. This work reports multilayer graphene (MLG) directly grown on SiO2 substrate at 300 °C by a novel pressure-assisted solid-phase diffusion synthesis method, and, for the first time, demonstrates a CMOS… 

Figures from this paper

Copper-graphene heterostructure for back-end-of-line compatible high-performance interconnects

Here, we demonstrate the fabrication of a Cu-graphene heterostructure interconnect by the direct synthesis of graphene on a Cu interconnect with an enhanced performance. Multilayer graphene films

Reliability and Performance of CMOS-Compatible Multi-Level Graphene Interconnects Incorporating Vias

Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects for extremely scaled dimensions [1],[2]. Even

Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias

Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional

Interconnect Technology/System Co-Optimization for Low-Power VLSI Applications Using Ballistic Materials

Promising interconnect materials continue to emerge and are considered as potential replacements for Cu interconnects. In this article, an interconnect technology/system codesign methodology is

Optoelectrical Operation Stability of Broadband PureGaB Ge-on-Si Photodiodes with Anomalous Al-Mediated Sidewall Contacting

An anomalous aluminum-mediated material transport process was investigated in sets of Ge-on-Si photodiodes with broadband optoelectrical characteristics measured at wavelengths from 255 nm to 1550

DESIGN AND EFFICIENCY ANALYSIS OF NANOCARBON INTERCONNECT STRUCTURES

  • Nirmal D Dr
  • Engineering
    Journal of Electronics and Informatics
  • 2019
With significant reduction in the size of ICs, there has been a massive increase in the operating speed. Due to this condition, the area available for interconnects within the transistor and between

High-Performance All-Optical Modulator Based on Graphene-HBN Heterostructures

Graphene has emerged as an ultrafast photonic material for on-chip all-optical modulation. However, its atomic thickness limits its interaction with guided optical modes, which results in a high

Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems

TLDR
A possible roadmap to enable CMOS compatible integration of 2-D materials and a particular emphasis on doping-free polarity-controllable systems that use electrostatic doping to eliminate the need for physical or chemical doping are described.

Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges

TLDR
2D materials provide a significantly better platform, with respect to bulk materials (such as Si, Ge, GaN), for realizing ultra-high-density M3D-ICs of ultimate thinness for next-generation electronics.

References

SHOWING 1-10 OF 16 REFERENCES

Intercalation Doped Multilayer-Graphene-Nanoribbons for Next-Generation Interconnects.

Copper-based interconnects employed in a wide range of integrated circuit (IC) products are fast approaching a dead-end due to their increasing resistivity and diminishing current carrying capacity

Characterization of self-heating and current-carrying capacity of intercalation doped graphene-nanoribbon interconnects

As VLSI technology node scales down beyond 14 nm, the current carrying capacity of metal interconnects decreases rapidly and will not meet the increasing circuit performance driven current density

Future on-chip interconnect metallization and electromigration

  • C. HuJ. Kelly F. Baumann
  • Materials Science
    2018 IEEE International Reliability Physics Symposium (IRPS)
  • 2018
TLDR
Data showed that Cu with Co cap, Co and Ru interconnects all had highly reliable electromigration, if the Cu liner cannot be scaled down below 2 nm in future interconnect technologies.

Global (interconnect) warming

This article presents a comprehensive analysis of the thermal effects in advanced high-performance VLSI interconnect systems arising due to self-heating under various circuit conditions, including

Low temperature critical growth of high quality nitrogen doped graphene on dielectrics by plasma-enhanced chemical vapor deposition.

TLDR
A critical factor for metal-free PECVD growth of NG is reported, which allows high quality NG crystals to be grown directly on dielectrics like SiO2/Si, Al2O3, h-BN, mica at 435 °C without a catalyst.

Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology

TLDR
Intrinsic TDDB reliability for Co/ low-k ILD meets the expectations and surpasses the capability of Cu/low- k ILD systems with E-field acceleration factor of ∼5 cm/MV using E-model fit.

Subtractive Etch of Ruthenium for Sub-5nm Interconnect

Ruthenium has been recently considered as a promising candidate to replace copper as the BEOL interconnect material for sub-5nm technology nodes. In this work, single level Ru interconnects were

Controllable and Rapid Synthesis of High-Quality and Large-Area Bernal Stacked Bilayer Graphene Using Chemical Vapor Deposition

Bilayer graphene has attracted wide attention due to its unique band structure and bandgap tunability under specific (Bernal or AB) stacking order. However, it remains challenging to tailor the

Remote catalyzation for direct formation of graphene layers on oxides.

TLDR
A novel growth technique that enables the direct deposition of graphene layers on SiO(2) with crystalline quality potentially comparable to graphene grown on Cu foils using chemical vapor deposition (CVD) rather than using Cu foil as substrates, which uses them to provide subliming Cu atoms in the CVD process.

Liquid exfoliation of defect-free graphene.

  • J. Coleman
  • Chemistry, Materials Science
    Accounts of chemical research
  • 2013
TLDR
This Account describes recent work to develop such a processing route inspired by previous theoretical and experimental studies on the solvent dispersion of carbon nanotubes, and extends this process to exfoliate other layered compounds such as BN and MoS(2).