CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI

  title={CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI},
  author={Junkai Jiang and Jae Hwan Chu and Kaustav Banerjee},
  journal={2018 IEEE International Electron Devices Meeting (IEDM)},
Cu interconnects suffer from steep rise in resistivity and severe reliability degradation for sub-20 nm line widths. Other metals, including Co and Ru, have been demonstrated with higher electromigration (EM) resistance, but exhibit lower electrical conductivity that degrades circuit performance. This work reports multilayer graphene (MLG) directly grown on SiO2 substrate at 300 °C by a novel pressure-assisted solid-phase diffusion synthesis method, and, for the first time, demonstrates a CMOS… 

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