CMOS Built-In Test Architecture for High-Speed Jitter Measurement

  title={CMOS Built-In Test Architecture for High-Speed Jitter Measurement},
  author={Henry C. Lin and Karen Taylor and Alan Chong and Eddie Chan and Mani Soma and Hosam Haggag and Jeffrey M. Huard and Jim Braatz},
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz I GHz input range with resolution of 70ps RMS jitter occupying 0.05 75mmz area. 
Highly Cited
This paper has 29 citations. REVIEW CITATIONS

From This Paper

Figures, tables, and topics from this paper.
19 Citations
7 References
Similar Papers


Publications citing this paper.
Showing 1-10 of 19 extracted citations


Publications referenced by this paper.
Showing 1-7 of 7 references

A four - channel selfcalibrating high - resolution time to digital converter ”

  • J. Christiansen
  • Proc . IEEE International Test Conference
  • 2001

A 1GSPS CMOS Flash A / D Converter for Systemon - chip Applications ”

  • K. Choi, J. Ghaznavi
  • IEEE Computer Society Workshop on VLSI

An Approach to Consistent Jitter Modeling for Various Jitter Aspects and Measurement Methods ”

  • A. Tangel

Similar Papers

Loading similar papers…