CMOS Built-In Test Architecture for High-Speed Jitter Measurement

@inproceedings{Lin2003CMOSBT,
  title={CMOS Built-In Test Architecture for High-Speed Jitter Measurement},
  author={Henry C. Lin and Karen Taylor and Alan Chong and Eddie Chan and Mani Soma and Hosam Haggag and Jeffrey M. Huard and Jim Braatz},
  booktitle={ITC},
  year={2003}
}
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz I GHz input range with resolution of 70ps RMS jitter occupying 0.05 75mmz area. 
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