CLIMATE (chip-level intertwined metal and active temperature estimator)

@article{Labun2003CLIMATEI,
  title={CLIMATE (chip-level intertwined metal and active temperature estimator)},
  author={A. Labun and Thomas Reeve},
  journal={International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.},
  year={2003},
  pages={23-26}
}
ULSI interconnect temperature is critical for electromigration risk assessment because of the exponential dependence of lifetime on temperature and for performance issues such as timing which are sensitive to temperature-dependent resistance. Steady state wire temperature is a function of Joule self-heating within the wire, heat conducted along the wire, and heat coupled from the active devices and other nearby wires through the dielectric. Chip-level estimates of wire temperatures for HP's… CONTINUE READING

Citations

Publications citing this paper.
Showing 1-2 of 2 extracted citations

References

Publications referenced by this paper.
Showing 1-5 of 5 references

One - Dimensional Estimation of Interconnect Temperatures

  • Andrew Labun, James Jensen
  • 2002

Thermal Conductance of IC Interconnects Embedded in Dielectrics

  • J. Gill Harmon, T. Sullivan
  • Integrated Reliability Workshop Final Report
  • 1998

iTEM : A Chip - Level Electromigration Reliability Diagnosis Tool Using Electrothermal Timing Simulation

  • Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sun-Mo Kang
  • International Reliability Physics Symposium
  • 1996

Similar Papers

Loading similar papers…