CLIMATE (chip-level intertwined metal and active temperature estimator)

  title={CLIMATE (chip-level intertwined metal and active temperature estimator)},
  author={A. Labun and Thomas Reeve},
  journal={International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.},
ULSI interconnect temperature is critical for electromigration risk assessment because of the exponential dependence of lifetime on temperature and for performance issues such as timing which are sensitive to temperature-dependent resistance. Steady state wire temperature is a function of Joule self-heating within the wire, heat conducted along the wire, and heat coupled from the active devices and other nearby wires through the dielectric. Chip-level estimates of wire temperatures for HP's… CONTINUE READING


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