CHESS: a comprehensive tool for CDFG extraction and synthesis of low power designs from VHDL

@article{Ranganathan2006CHESSAC,
  title={CHESS: a comprehensive tool for CDFG extraction and synthesis of low power designs from VHDL},
  author={N. Ranganathan and Ravi Namballa and Narender Hanchate},
  journal={IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)},
  year={2006},
  pages={6 pp.-}
}
In this paper, a new tool CHESS, is designed and developed for control and data-flow graph (CDFG) extraction and the high level synthesis of low power designs from behavioral level VHDL descriptions. The tool optimizes latency, area and power during the different phases of synthesis and provides several solutions to evaluate the trade-offs during design. Unlike the case of DFGs, not much work has been reported in the literature for low power synthesis of CDFGs. The tool consists of three… CONTINUE READING

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