CESC: a visual formalism for specification and verification of SoCs

@inproceedings{Gadkari2004CESCAV,
  title={CESC: a visual formalism for specification and verification of SoCs},
  author={Ambar A. Gadkari and S. Ramesh and Rubin A. Parekhji},
  booktitle={ACM Great Lakes Symposium on VLSI},
  year={2004}
}
Verification of present day SoCs is proving to be challenging due to complex interactions among various subcomponents and IPs, with multiple clock domains and diverse bus protocols. The quality of verification depends on the precision in specifying the interaction behaviors. We propose a visual specification language called CESC (Clocked Event Sequence Chart), designed to specify interaction scenarios in SoCs. CESC provides a unique mechanism for representating multiple clock domains, based… CONTINUE READING