CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits

@article{Zhou2007CASCADEAS,
  title={CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits},
  author={Lili Zhou and Cherry Wakayama and C.-J. Richard Shi},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2007},
  volume={26},
  pages={1270-1282}
}
In this paper, CASCADE, a standard supercell-based design methodology, its supporting automated design flow, and associated design tools, are presented for 3D implementations of a class of interconnect-heavy application-specific very large-scale integrated circuits. In CASCADE, a system is first partitioned and synthesized using standard 2D design tools to a set of supercells with the same height and varying widths. With this, the 3D design is reduced to 3D supercell placement and 3D-via… CONTINUE READING

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