CAD Techniques for Power Optimization in Virtex-5 FPGAs

@article{Gupta2007CADTF,
  title={CAD Techniques for Power Optimization in Virtex-5 FPGAs},
  author={Subodh Gupta and Jason Helge Anderson and Linda Farragher and Qiang Wang},
  journal={2007 IEEE Custom Integrated Circuits Conference},
  year={2007},
  pages={85-88}
}
We consider dynamic power dissipation in FPGAs and present CAD techniques for dynamic power reduction. The proposed techniques, comprising power-aware placement, routing, and a novel post-routing transformation, are applied to optimize the power consumed by industrial designs implemented in the Xilinxreg Virtextrade-5 FPGA. Board-level power measurements on a suite of industrial designs show that the techniques reduce power by 10%, on average. 
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