CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory

@article{Chen2012CACTI3DDAM,
  title={CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory},
  author={K X Chen and Sheng Li and Naveen Muralimanohar and Jung Ho Ahn and Jay B. Brockman and Norman P. Jouppi},
  journal={2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
  year={2012},
  pages={33-38}
}
Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future memory architectures to satisfy the ever-increasing demands on performance, power, and cost. This paper introduces CACTI-3DD, the first architecture-level integrated power, area, and timing modeling framework for 3D die-stacked off-chip DRAM main memory. CACTI-3DD includes TSV models, improves models for 2D off-chip DRAM main memory over current versions of CACTI, and includes 3D integration models that… CONTINUE READING
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