Built-in self repair by reconfiguration of FPGAs

  title={Built-in self repair by reconfiguration of FPGAs},
  author={S. Habermann and Ren{\'e} Kothe and Heinrich Theodor Vierhaus},
  journal={12th IEEE International On-Line Testing Symposium (IOLTS'06)},
  pages={2 pp.-}
Systems on a chip (SoCs) in safety-critical applications need features such as built-in self-test, on-line self-test and error compensation of transient faults. With ever-shrinking feature size, also built-in self-repair (BISR) may become a must. While BIST and BISR are well understood and frequently implemented for embedded memory blocks, BISR for random logic is by far an unsolved problem. Logic circuits based on field-programmable gate arrays (FPGAs) are a technology base that allows for… CONTINUE READING
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