Buffer planning for application-specific networks-on-chip design


Networks-on-chip (NoC) is a promising communication architecture for next generation SoC. The size of buffer used in on-chip routers impacts the silicon area and power consumption of NoC dominantly. It is important to plan the total buffer-size and each router buffer-allocation carefully for an efficient NoC design. In this paper, we propose two buffer planning algorithms for application-specific NoC design. More precisely, given the traffic parameters and performance constraints of target application, the proposed algorithms automatically determine minimal buffer budget and assign the buffer depth for each input channel in different routers. The experimental results show that the proposed algorithms can significantly reduce total buffer usage and guarantee the performance requirements.

DOI: 10.1007/s11432-009-0085-x

17 Figures and Tables

Cite this paper

@article{Yin2009BufferPF, title={Buffer planning for application-specific networks-on-chip design}, author={Shouyi Yin and Leibo Liu and Shaojun Wei}, journal={Science in China Series F: Information Sciences}, year={2009}, volume={52}, pages={547-558} }