• Corpus ID: 18504081

Broadcom Shows off New Cpu Brcm 5000 Provides Dual Issue, Multithreading for Broadband Chips Generations of Cpu Development

@inproceedings{GwennapBroadcomSO,
  title={Broadcom Shows off New Cpu Brcm 5000 Provides Dual Issue, Multithreading for Broadband Chips Generations of Cpu Development},
  author={Linley Gwennap}
}

• L. Gwennap
• Computer Science

One should not light a candle and hide it under a bushel, but rather place it where all can see its light. For years, Broadcom has developed its own CPUs and hidden them inside a variety of system-on-a-chip (SoC) products. Recently, the company provided documentation on these CPUs exclusively to Microprocessor Report, allowing us to reveal its accomplishments for all to see. These documents provide an in-depth portrayal of an entire family of CPUs, culminating in the most recent design, the BRCM 5000 (code-named Zephyr). The 5000 is a superscalar MIPS32 CPU that supports two threads for increased performance. The design uses a 12-stage pipeline to achieve a production speed of 1.3GHz. It supports a dual-level cache subsystem and can be combined into a dual-CPU configuration for a total of four threads. This level of performance is well suited to emerging set-top boxes (STBs) and other high-end consumer products. The initial 5000-based products, including the BCM7420 processor, entered production in 65nm LP in 3Q09. The first 40nm BRCM 5000 products entered production in 4Q10. Broadcom has four major business units: enterprise, broadband, connectivity, and mobile. The latter two rely on ARM CPUs, because of their focus on low power and the large base of ARM software in the mobile market. For these products, the company licenses ARM CPU cores. For enterprise and broadband, however, Broadcom has relied extensively on MIPS CPUs. Although it has licensed some MIPS cores, the company has a long history of developing its own CPUs and today uses these CPUs for all of its broadband products, including DSL, cable-modem, fiber, STB, and digital-TV (DTV) chips. (Some of these products include MIPS-designed CPUs as well.) These broadband products generate more than $2 billion in annual revenue. Broadcom's CPU development stretches back more than 10 years, when the company shipped its first DSL chip with an internally designed CPU, now known as the BRCM 3300 core. This CPU, which the company still uses today, is quite small (less than 1mm 2 in 40nm CMOS, including cache), making it ideal for low-cost products such as ADSL chips. The simple scalar CPU uses a six-stage pipeline to achieve clock speeds of 700MHz in 40nm G, as Figure 1 shows. It generally uses 32KB of instruction cache and 16KB of data cache, although the synthesizable design can be configured in multiple ways. The small data cache is optimized for broadband applications, …