Broadcast scan compression based on deterministic pattern generation algorithm

Abstract

As advances in technology make integrating more transistors on a single integrated circuit (IC) feasible, test data volume becomes one of major factors of testing systemon-chips (SoCs). The large volume of test data leads to increasing test application time and needs more expensive Automatic test equipment (ATE) with high memory. In this paper, we present broadcast scan compression based on deterministic pattern generation algorithm to reduce the volume of test data. The proposed method further improves compression ratio of the volume of test data by exploiting advances of both broadcast scan compression and pattern generation using linear feedback shift register (LFSR). The volume of test data can be reduced by feeding multiple scan chains from a few LFSRs and by compressing the data using LFSRs. ISCAS’89 benchmark circuits verify the proposed method and the experimental results show that the compression ratio is up to 10X which means test application time also is reduced extremely.

DOI: 10.1109/ISQED.2017.7918357

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Cite this paper

@inproceedings{Lim2017BroadcastSC, title={Broadcast scan compression based on deterministic pattern generation algorithm}, author={Hyeonchan Lim and Sungyoul Seo and Soyeon Kang and Sungho Kang}, booktitle={ISQED}, year={2017} }