Bringing communication networks on a chip: test and verification implications

@article{Vermeulen2003BringingCN,
  title={Bringing communication networks on a chip: test and verification implications},
  author={Bart Vermeulen and John Dielissen and Kees G. W. Goossens and Calin Ciordas},
  journal={IEEE Communications Magazine},
  year={2003},
  volume={41},
  pages={74-81}
}
In this article we present test and verification challenges for system chips that utilise on-chip networks. These systems on a chip ( SOCs) and networks on a chip ( NOCs) are introduced, where the NOC is exemplified by Philips’s ÆTHEREAL NOC architecture. We discuss existing test and verification methods for SOCs andNOCs, and show the particular advantages of using a NOC both for testing and verifying the network, and for testing and verifying the other components of the SOC. This paper is… CONTINUE READING
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