DC holding and dynamic triggering characteristics of bulk CMOS latch-up,
- R . D. Rung, H. Momose
- IEEE Trans. Elecrron Devices, vol. ED-30,
The aim of this brief is to present an original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up.