Branching-Time Temporal Logics with Minimal Model Quantifiers

  title={Branching-Time Temporal Logics with Minimal Model Quantifiers},
  author={Fabio Mogavero and Aniello Murano},
  booktitle={Developments in Language Theory},
Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the correctness of a system with respect to its desired behavior (specification), by verifying whether a model of the system satisfies a temporal logic formula modeling the specification. From a practical point of view, a very challenging issue in using temporal logic in formal verification is to come out with techniques that… 

Logics in Computer Science

Four new temporal logic formalisms that can be used as specification languages for the automated verification of the reliability of hardware and software designs with respect to a desired behavior are introduced and examined.

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Conformance Tester for STP-ISS Protocol Implementation Based on Formal Model

  • N. ChumakovaV. Olenev
  • Computer Science
    2018 Wave Electronics and its Application in Information and Telecommunication Systems (WECONF)
  • 2018
This paper presents Software-to-hardware Tester, intended for conformance testing of STP-ISS-13 protocol implementation, based on a formal model, which considers a process of conformation testing by means of computational tree temporal logic and a compilation example of temporal logic formula for a protocol requirement.



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Modular Model Checking

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