Corpus ID: 44461629

Bounds on Bus and Memory Interference in a class of Multiple Bus Multiprocessor Systems

  title={Bounds on Bus and Memory Interference in a class of Multiple Bus Multiprocessor Systems},
  author={M. A. Marson},
BUS AND CACHE MEMORY ORGANIZATIONS FOR MULTIPROCESSORS by Donald Charles Winsor Chairman: Trevor Mudge The single shared bus multiprocessor has been the most commercially successful multiprocessor system design up to this time, largely because it permits the implementation of efficient hardware mechanisms to enforce cache consistency. Electrical loading problems and restricted bandwidth of the shared bus have been the most limiting factors in these systems. This dissertation presents designs… Expand
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  • 1984
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