Corpus ID: 44461629

Bounds on Bus and Memory Interference in a class of Multiple Bus Multiprocessor Systems

@inproceedings{Marson1982BoundsOB,
  title={Bounds on Bus and Memory Interference in a class of Multiple Bus Multiprocessor Systems},
  author={M. A. Marson},
  booktitle={ICDCS},
  year={1982}
}
BUS AND CACHE MEMORY ORGANIZATIONS FOR MULTIPROCESSORS by Donald Charles Winsor Chairman: Trevor Mudge The single shared bus multiprocessor has been the most commercially successful multiprocessor system design up to this time, largely because it permits the implementation of efficient hardware mechanisms to enforce cache consistency. Electrical loading problems and restricted bandwidth of the shared bus have been the most limiting factors in these systems. This dissertation presents designs… Expand
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References

SHOWING 1-10 OF 22 REFERENCES
M-users B-servers arbiter for multiple-busses multiprocessors
TLDR
To increase the speed of arbitration a design with two levels of lookahead is proposed, which can be used effectively for up to 16 processors, memory modules and busses. Expand
Dynamic decentralized cache schemes for mimd parallel processors
TLDR
It appears that moderately large parallel processors can be designed by employing the principles presented in this paper, and both schemes feature decentralized consistency control and dynamic type classification of the datum cached. Expand
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors
TLDR
The effective bandwidth in a multiprocessor with shared memory with N processors and N memory modules is compared using as interconnection networks the crossbar or the multiple-bus. Expand
Using cache memory to reduce processor-memory traffic
TLDR
It is demonstrated that a cache exploiting primarily temporal locality (look-behind) can indeed reduce traffic to memory greatly, and introduce an elegant solution to the cache coherency problem. Expand
An analysis of the instruction execution rate in certain computer structures
TLDR
A simple automatic design program is proposed which optimally configures computer structures from a set of available components and relates the instruction execution rate to the memory and processor speeds, their number, and their interconnection. Expand
Interference in multiprocessor computer systems with interleaved memory
TLDR
The model results provide a good indication of the performance that should be expected from real systems of this type and suggest that the results are valid for a much larger class of models, including those more nearly like real systems than the simple model. Expand
Experimental evaluation of on-chip microprocessor cache memories
TLDR
This paper uses trace driven simulation to study design tradeoffs for small (on-chip) caches, and finds that general purpose caches of 64 bytes (net size) are marginally useful in some cases, while 1024-byte caches perform fairly well. Expand
Performance Analysis of Future Shared Storage Systems
TLDR
This paper deals with the analysis and design of two important classes of computer systems: BIP (Billion Instructions Per Second) systems consisting of a few very high performance processors and KMIP systems with hundreds of low speed processors. Expand
Analysis of Memory Interference in Multiprocessors
TLDR
This paper presents Markov chain models for analyzing the extent of memory interference in multiprocessor systems with a crosspoint switch for processor-memory communication and the results predicted are compared with some simulation results and some actual measurements on C.mmp, a multipROcessor system being built at Carnegie-Mellon University. Expand
A General Model for Memory Interference in Multiprocessors
This paper presents a mathematical model for determining the extent of memory interference in multiprocessor systems. The model takes into account the numbers of processors and memory modules in theExpand
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