Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity

@article{Darabiha2008BlockInterlacedLD,
  title={Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity},
  author={Ahmad Darabiha and Anthony Chan Carusone and Frank R. Kschischang},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2008},
  volume={55},
  pages={74-78}
}
Two design techniques are proposed for high-throughput low-density parity-check (LDPC) decoders. A broadcasting technique mitigates routing congestion by reducing the total global wirelength. An interlacing technique increases the decoder throughput by processing two consecutive frames simultaneously. The brief discusses how these techniques can be used for both fully parallel and partially parallel LDPC decoders. For fully parallel decoders with code lengths in the range of a few thousand bits… CONTINUE READING
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