Bitwise data parallelism in regular expression matching

@article{Cameron2014BitwiseDP,
  title={Bitwise data parallelism in regular expression matching},
  author={Robert D. Cameron and Thomas C. Shermer and Arrvindh Shriraman and Kenneth S. Herdy and Dan Lin and Benjamin R. Hull and Meng Lin},
  journal={2014 23rd International Conference on Parallel Architecture and Compilation (PACT)},
  year={2014},
  pages={139-150},
  url={https://api.semanticscholar.org/CorpusID:2193114}
}
A new parallel algorithm for regular expression matching is developed and applied to the classical grep (global regular expression print) problem and can substantially outperform traditional grep implementations based on NFAs, DFAs or backtracking.
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30 References

High-performance regular expression scanning on the Cell/B.E. processor

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Several techniques are introduced to do optimization on GPUs, including reducing global memory transactions of input buffer, reducing latency of transition table lookup, eliminating output table accesses, avoiding bank-conflict of shared memory, coalescing writes to global memory, and enhancing data transmission via peripheral component interconnect express.

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Faster Regular Expression Matching

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A Bit-Parallel Approach to Suffix Automata: Fast Extended String Matching

A new algorithm for string matching called BNDM, which is the bit-parallel simulation of a known (but recent) algorithm called BDM, and which can be extended to handle classes of characters in the pattern and in the text, multiple patterns and to allow errors in thepattern or in thetext, combining simplicity, efficiency and flexibility.

Data-parallel finite-state machines

This paper describes a parallel algorithm for FSMs that breaks dependences across iterations by efficiently enumerating transitions from all possible states on each input symbol, which allows the algorithm to utilize various sources of data parallelism available on modern hardware, including vector instructions and multiple processors/cores.

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Parabix: Boosting the efficiency of text processing on commodity processors

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