Bitstream compression techniques for Virtex 4 FPGAs

Abstract

This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardware implementation cost. As our purpose is the acceleration of the configuration process, estimating the decoder speed also plays a major role in our study. We evaluate a wide range… (More)
DOI: 10.1109/FPL.2008.4629952

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