Bitstream-based simulation for configuration SEUs in Xilinx Virtex-4 FPGAs

Abstract

Bitstream-based simulation approach was proposed and experimentally validated by heavy ions and protons in Xilinx Virtex-4 FPGAs. The simulation approach is able to predict the probability of an SEU to reduce a functional failure. With the existence of the SEU sensitivity data of the configuration memories, the functional failure probability of any… (More)

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