Corpus ID: 17892355

Bit Serial Architecture for the Two-Dimensional DCT

@inproceedings{Snchez1995BitSA,
  title={Bit Serial Architecture for the Two-Dimensional DCT},
  author={M. S{\'a}nchez and J. Bruguera and E. Zapata},
  year={1995}
}
  • M. Sánchez, J. Bruguera, E. Zapata
  • Published 1995
  • Computer Science
  • We present an architecture for the calculation of the Two Dimensional Discrete Cosine Transform and its Inverse that admits a high data rate. It is based on the row-column decomposition, the use of a fast algorithm, serial digit arithmetic and redundant coding. The critical path is set by the delay of a multiplexer plus a binary adder with as many digits as the width of the serial digits to be processed. We discuss its implementation for processing 8 bit 8x8 pixel blocks or 12 bit coefficients… CONTINUE READING
    1 Citations

    References

    SHOWING 1-7 OF 7 REFERENCES
    CMOS VLSI implementation of the 2D-DCT with linear processor arrays
    • 33
    A one chip VLSI for real time two-dimensional discrete cosine transform
    • 36
    VLSI implementation of a 16*16 discrete cosine transform
    • 212
    A single chip video rate 16×16 discrete cosine transform
    • 25
    Discrete Cosine Transform
    • 3,642
    • Highly Influential
    • PDF
    otros, "A 100-MHz 2D Discrete Cosine Transform Core Processor
    • IEEE Joornal of Solid- StateCircuits,
    • 1992
    Sicre, "TCAD; A 27 MHZ 8x8 discrete cosine transform chip,
    • Intl. Conf. on Acoust. , Speech, Signal Process,
    • 1989