Corpus ID: 17892355

Bit Serial Architecture for the Two-Dimensional DCT

@inproceedings{Snchez1995BitSA,
  title={Bit Serial Architecture for the Two-Dimensional DCT},
  author={M. S{\'a}nchez and J. Bruguera and E. Zapata},
  year={1995}
}
  • M. Sánchez, J. Bruguera, E. Zapata
  • Published 1995
  • Computer Science
    • We present an architecture for the calculation of the Two Dimensional Discrete Cosine Transform and its Inverse that admits a high data rate. It is based on the row-column decomposition, the use of a fast algorithm, serial digit arithmetic and redundant coding. The critical path is set by the delay of a multiplexer plus a binary adder with as many digits as the width of the serial digits to be processed. We discuss its implementation for processing 8 bit 8x8 pixel blocks or 12 bit coefficients… CONTINUE READING
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    Low power VLSI implementation schemes for DCT-based image compression

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