Bit-Level Analysis of an SRT Divider Circuit

@inproceedings{Bryant1996BitLevelAO,
  title={Bit-Level Analysis of an SRT Divider Circuit},
  author={Randal E. Bryant},
  booktitle={DAC},
  year={1996}
}
It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered binary decision diagrams (BDDs), because the BDD representations for these functions grow exponentially with the word size. It is possible, however, to analyze individual stages of these circuits using BDDs. Such analysis can be helpful when implementing complex arithmetic algorithms. As a demonstration, we show that Intel could have used BDDs to detect erroneous lookup table entries in the… CONTINUE READING

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