Binary Decision Diagrams

@article{Akers1978BinaryDD,
  title={Binary Decision Diagrams},
  author={Sheldon B. Akers},
  journal={IEEE Transactions on Computers},
  year={1978},
  volume={C-27},
  pages={509-516}
}
  • S. Akers
  • Published 1 June 1978
  • Computer Science
  • IEEE Transactions on Computers
This paper describes a method for defining, analyzing, testing, and implementing large digital functions by means of a binary decision diagram. This diagram provides a complete, concise, "implementation-free" description of the digital functions involved. Methods are described for deriving these diagrams and examples are given for a number of basic combinational and sequential devices. Techniques are then outlined for using the diagrams to analyze the functions involved, for test generation… Expand
Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams
TLDR
This correspondence presents a test generation methodology for VLSI circuits described at the functional level, which proposes a generalized D algorithm for generating tests to detect functional as well as gate-level faults. Expand
Functional test generation using binary decision diagrams
TLDR
A generalization of the D-algorithm is proposed which takes the module-level model and the functional description of the modules as parameters, and generates tests to detect the faults in the fault model. Expand
Verification algorithms for VLSI synthesis
  • G. Hachtel, R. Jacoby
  • Mathematics, Computer Science
  • IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
  • 1988
TLDR
Experimental results are given which indicate that, with the exception of the don't-care method, each of these methods has a problem class in which it is clearly superior to the others. Expand
The use of binary decision diagrams for the decomposition of programmable logic arrays
The decomposition method of programmable logic arrays based on the two-block partitioning of a set of variables and the algorithm of the selection of variable partitioning are suggested. The methodExpand
Binary Decision Diagrams: From Abstract Representations to Physical Implementations
TLDR
The paper shows that further significant benefits can be realized by implementing BDDs as custom or semi-custom integrated circuits, including efficient use of silicon area and improved simulation. Expand
Ternary decision diagrams
TLDR
This paper describes a method of defining, analyzing, and implementing the Boolean function using a ternary decision diagram (TDD), which enables us to evaluate a Boolean function. Expand
An Enhanced Algorithm for Variable Reordering in Binary Decision Diagrams
  • C. Varma
  • Computer Science
  • 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT)
  • 2018
TLDR
This paper outlines an enhanced variable ordering algorithm which shall be capable to produce the minimum number of nodes for a given Reduced Ordered Binary Decision Diagrams (ROBDD). Expand
A Characterization of Binary Decision Diagrams
TLDR
A tighter bound on the size of an ordered BDD that can be computed from a given Boolean circuit is presented and a case is made for exploring the use of repeated BDDs, with a small number of repeated variables, and free BDD's for some applications for which only ordered B DDs have been used so far. Expand
Use of binary decision diagrams in the modelling and synthesis of binary multipliers
  • K. D. Lamb
  • Computer Science
  • Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit
  • 1996
TLDR
This paper presents a method of partitioning the multiplier in a manner which restricts the complexity to the carry bits, which results in BDD's which grow no faster than the square of the number of inputs. Expand
Algorithms for technology mapping based on binary decision diagrams and on Boolean operations
TLDR
Algorithms and a computer-aided design tool for technology mapping of both completely specified and incompletely specified logic networks are introduced and a novel matching algorithm, using ordered binary decision diagrams, is described. Expand
...
1
2
3
4
5
...

References

SHOWING 1-10 OF 13 REFERENCES
On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets
  • D. Armstrong
  • Engineering, Computer Science
  • IEEE Trans. Electron. Comput.
  • 1966
TLDR
A procedure is described for finding, by shortcut methods, a near-minimal set of tests for detecting all single faults in a combinational logic net, and it is shown that if a set of Tests can be found which detects an appropriate subset of faults in the enf, this set will detect all faults inThe original net. Expand
Complete Test Sets for Logic Functions
  • S. Reddy
  • Mathematics, Computer Science
  • IEEE Transactions on Computers
  • 1973
TLDR
It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any number of stuck-at-faults in a network belonging to a class of restricted networks, called unate gate networks. Expand
Multi-threshold threshold elements
  • D. R. Haring
  • Mathematics, Computer Science
  • IEEE Trans. Electron. Comput.
  • 1966
TLDR
It is proved that if the given function requires a k-threshold threshold element, then at least [k/2+I] conventional threshold elements in a two-level network or [1+log 2 k] such elements inA multilevel network are required. Expand
Universal Test Sets for Logic Networks
  • S. Akers
  • Mathematics, Computer Science
  • IEEE Trans. Computers
  • 1973
TLDR
It is shown that, for AND/OR networks, universal test sets may be found that detect not only all single faults but all multiple faults as well. Expand
fundamental algorithms
TLDR
General Instructions Material: You may only use one handwritten sheet of paper (size A4, on both pages) to solve the exercises and any other material including electronic devices of any kind is forbidden. Expand
Advanced Micro Devices Data Book
  • 1974
Structural Models: An Introduction to the Theory of Directed Graphs
The Theory of Graphs and Its Applications.
...
1
2
...