Beyond Write-Reduction Consideration: A Wear-Leveling-Enabled B⁺-Tree Indexing Scheme Over an NVRAM-Based Architecture

@article{Dharamjeet2021BeyondWC,
  title={Beyond Write-Reduction Consideration: A Wear-Leveling-Enabled B⁺-Tree Indexing Scheme Over an NVRAM-Based Architecture},
  author={. Dharamjeet and Tseng-Yi Chen and Yuan-Hao Chang and Chun-Feng Wu and Chi-Heng Lee and W. K. Shih},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2021},
  volume={40},
  pages={2455-2466}
}
  • .. Dharamjeet, Tseng-Yi Chen, W. Shih
  • Published 1 December 2021
  • Computer Science
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Recently, nonvolatile random-access memory (NVRAM) has been regarded as the most up-and-coming main memory technology in embedded and Internet-of-Things (IoT) systems due to its attractive features: zero-static power consumption and high memory cell density. However, the endurance issue as a “nightmare” always haunts NVRAM system developers. Worse still, NVRAM’s lifespan will wear out soon in embedded applications because their data management systems usually utilize an indexing scheme to…