Introduction Cell-based layout systems are widely used for automatic physical design of large digital systems. Standard cell and gate array layout systems are reaching a state of maturity: small differences in layout effectiveness are used to distinguish commercially available systems. General cell and mixed standard cell and general cell layout systems have moved from research projects to general availability. Even with this widespread use and the many publications of cell-based layout systems, no recognized benchmarks are available to form the basis of comparison and evaluation. In addition to the difficulty of comparing layout systems, algorithm research is hampered by the lack of recognized benchmark examples. It is very difficult to evaluate published algorithms because common examples are not used. Potentially promising algorithms have been denied publication because some researchers do not have access to real circuit descriptions. Random or contrived examples are, to a large number of reviewers, no longer acceptable for journal and conference publication. For some problems, publication of examples is sufficient to establish industry wide benchmarks; channel and switchbox routing are examples. However, cell-based layout problems are much too complex for such casual methods. Practical circuits may have several thousand cells, and circuits with over 10,000 cells are reported with some regularity. For such circuits, the parts list and the interconnection list may require a substantial fraction of a megabyte for storage. In addition to large size, the complexity of the cell libraries and the design rules inhibit sharing of layout examples. This panel wiH consider the benefits, problems and challenges of creating, distributing and maintaining a representative set of benchmarks for cell-based layout systems.
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