Corpus ID: 219636112

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking

  title={Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking},
  author={Benjamin Tan and R. Karri and Nimisha Limaye and Abhrajit Sengupta and O. Sinanoglu and Md. Moshiur Rahman and S. Bhunia and Danielle Duvalsaint and R. Blanton and Amin Rezaei and Yuanqi Shen and H. Zhou and Leon Li and A. Orailoglu and Zhaokun Han and Austin Benedetti and Luciano Brignone and Muhammad Yasin and J. Rajendran and Michael Zuzak and A. Srivastava and Ujjwal Guin and C. Karfa and K. Basu and Vivek V. Menon and M. French and P. Song and F. Stellari and Gi-Joon Nam and P. Gadfort and Alric Althoff and J. Tostenrude and Saverio Fazzari and E. Breckenfeld and Kenneth Plaks},
Integrated circuits (ICs) are the foundation of all computing systems. They comprise high-value hardware intellectual property (IP) that are at risk of piracy, reverse-engineering, and modifications while making their way through the geographically-distributed IC supply chain. On the frontier of hardware security are various design-for-trust techniques that claim to protect designs from untrusted entities across the design flow. Logic locking is one technique that promises protection from the… Expand
State of the Art on: IP Protection through Logic Locking at Register-Transfer Level
The scaling of semiconductor technology with the associated rise of fabrication costs has limited the number of companies that can afford the billion-dollar manufacturing foundries. With thisExpand
Research Project Proposal: IP Protection through Logic Locking at Register-Transfer Level
The integrated circuit (IC) supply chain is the process that realizes a physical chip starting from its design. The entire process is becoming more and more distributed across different parties [8].Expand
Adaptable and Divergent Synthetic Benchmark Generation for Hardware Security
  • Sarah Amir, Domenic Forte
  • Computer Science
  • 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
  • 2020
This paper describes the first synthetic benchmark generation process flow that utilizes linear optimization to generate an endless number of synthetic combinational benchmarks that are adaptable to user input constraints and divergent in quantifiable structural features from input reference benchmarks. Expand
ASSURE: RTL Locking Against an Untrusted Foundry
A cost and security assessment of ASSURE against state-of-the-art oracle-less attacks is performed and it is found that the RTL approach has three advantages: it allows designers to obfuscate IP cores generated with many different methods, and it does not require modifications to EDA flows. Expand
Quantifying the Efficacy of Logic Locking Methods
This work develops a flow for approximating key corruption and minimum corruption, that capture the goals of locking under different attack scenarios on generic locked circuits and evaluates several locking techniques. Expand


The End of Logic Locking? A Critical View on the Security of Logic Locking
It is argued that there are strong indications that logic locking will most likely never be secure against a determined malicious foundry, and an attacker model is derived that matches reality, yielding attacks against the foundations of locking schemes beyond the usually employed SAT-based attacks. Expand
Provably-Secure Logic Locking: From Theory To Practice
This paper proposes stripped-functionality logic locking (SFLL), which strips some of the functionality of the design and hides it in the form of a secret key(s), thereby rendering on-chip implementation functionally different from the original one. Expand
Piercing Logic Locking Keys through Redundancy Identification
  • L. Li, A. Orailoglu
  • Computer Science
  • 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
  • 2019
An attack algorithm is developed that prunes out the incorrect value of each key bit when it introduces a significant level of logic redundancy, thus exposing vulnerabilities at the earliest stage even for applications that seek refuge from attacks through functional opaqueness. Expand
Defense-in-Depth: A Recipe for Logic Locking to Prevail
Adefense-in-depth is a multilayer defense approach where several independent countermeasures are implemented in the device to provide aggregated protection against different attack vectors in logic locking. Expand
ATPG-based cost-effective, secure logic locking
It is shown how VLSI testing principles and tools can be adopted to automate critical steps in SFLL and minimize its cost, and a proposed SFLL-fault that utilizes fault injection driven synthesis to efficiently explore design options and ATPG to assess security levels is proposed. Expand
Characterization of Locked Sequential Circuits via ATPG
An oracle-free, ATPG-based approach is proposed for characterizing the security of a locked sequential circuit, and is effective at recovering the key sequence from various sequentially locked circuits that have been locked using different locking methods. Expand
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective
A revised version of SFLL, namely SFLL-rem, is presented, that not only retains all security properties ofSFLL but also delivers resilience to all the state-of-the-art attacks SFLL can thwart, but also to the latest removal attacks that broke some SFLL instances. Expand
Keynote: A Disquisition on Logic Locking
The evolution of logic locking over the last decade is surveyed and various “cat-and-mouse” games involved in logic locking along with its novel applications—including, processor pipelines, graphics processing units (GPUs), and analog circuits are introduced. Expand
What to Lock?: Functional and Parametric Locking
This paper proposes a tenacious and traceless logic locking technique, TTlock, that locks functionality and provably withstands all known attacks, such as SAT-based, sensitization, removal, etc. Expand
Towards provably-secure performance locking
This paper develops provably-secure performance locking, where only on applying the correct key the IC shows superior performance; for an incorrect key, the performance of the IC degrades significantly. Expand