Behavioral-level test vector generation for system-on-chip designs

@article{Lajolo2000BehaviorallevelTV,
  title={Behavioral-level test vector generation for system-on-chip designs},
  author={M. Lajolo and M. Rebaudengo and M. Reorda and M. Violante and L. Lavagno},
  journal={Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)},
  year={2000},
  pages={21-26}
}
  • M. Lajolo, M. Rebaudengo, +2 authors L. Lavagno
  • Published 2000
  • Computer Science
  • Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)
  • Co-design tools represent an effective solution for reducing costs and shortening time-to-market, when system-on-chip design is considered. In a top-down design flow, designers would greatly benefit from the availability of tools able to automatically generate test sequences, which can be reused during the following design steps, from the system-level specification to the gate-level description. This would significantly increase the chance of identifying testability problems early in the design… CONTINUE READING
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