Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control

@article{Chuang2009BandwidthefficientCM,
  title={Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control},
  author={Tzu-Der Chuang and Lo-Mei Chang and Tsai-Wei Chiu and Yi-Hau Chen and Liang-Gee Chen},
  journal={2009 IEEE International Conference on Acoustics, Speech and Signal Processing},
  year={2009},
  pages={2009-2012}
}
For H.264/AVC decoder system, the motion compensation bandwidth comes from two parts, the reference data loading bandwidth and the equivalent bandwidth from DRAM access overhead latency. In this paper, a bandwidth-efficient cache-based MC architecture is proposed. It exploits both intra-MB and inter-MB data reuse and reduce up to 46% MC bandwidth compared to conventional scheme. To reduce the equivalent bandwidth from DRAM access overhead latency, the DRAM-friendly data mapping and access… CONTINUE READING
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