Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism

@article{Berg2008BandwidthAF,
  title={Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism},
  author={Ardy van den Berg and Pengwei Ren and Erik Jan Marinissen and Georgi Gaydadjiev and Kees G. W. Goossens},
  journal={2008 13th European Test Symposium},
  year={2008},
  pages={21-26}
}
Test data travels through a System-on-Chip (SOC) from the chip pins to the module-under-test and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented with dedicated wires. However, also existing functional interconnect, such as a bus or Network-on-Chip (NOC), can be reused as TAM. This will reduce the overall design effort and the silicon area. For a given module, its test set, and maximal bandwidth that the functional interconnect can offer between ATE and module… CONTINUE READING

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Key Quantitative Results

  • Experimental results show an average bandwidth utilization of 80%, while the remaining 20% is consumed by the idle bits.1 Introduction Rapid improvements in the semiconductor industry allow the design and manufacturing of increasingly complex chips, often referred to as SOCs.

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