Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor

@article{Zhang2017BalancingPA,
  title={Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor},
  author={Mingzhe Zhang and Lunkai Zhang and Lei Jiang and Zhiyong Liu and Frederic T. Chong},
  journal={2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)},
  year={2017},
  pages={385-396}
}
Multi Level Cell (MLC) Phase Change Memory (PCM) is an enhancement of PCM technology, which provides higher capacity by allowing multiple digital bits to be stored in a single PCM cell. However, the retention time of MLC PCM is limited by the resistance drift problem and refresh operations are required. Previous work shows that there exists a trade-off between write latency and retention—a write scheme with more SET iterations and smaller current provides a longer retention time but at the cost… CONTINUE READING

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