A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI circuit has become a major constrain in a battery operated device for technology node below 90nm, as it drains the battery even when a circuit is in standby mode. Major concern is the leakage even in run time condition, here aim is to focus on run time leakage reduction technique of integrated Circuit. It is inherited by stacking effect when the series transistors are maximized in OFF state condition. This method is independent of process technology and does not require any additional power supply. This paper gives an optimized solution of input pattern determination of some small circuit to find minimum leakage vector considering promising and non-promising node which helps to reduce the time complexity of the algorithm. Proposed algorithm is simulated using HSPICE simulator for 2 input NAND gate and different standard logic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell and different logics respectively.