Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology

@article{Abbas2016BacksideIS,
  title={Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology},
  author={Tarek Al Abbas and Neale A. W. Dutton and Oscar Almer and Sara Pellegrini and Yann Henrion and R. K. Henderson},
  journal={2016 IEEE International Electron Devices Meeting (IEDM)},
  year={2016},
  pages={8.1.1-8.1.4}
}
We present the first 3D-stacked backside illuminated (BSI) single photon avalanche diode (SPAD) image sensor capable of both single photon counting (SPC) intensity, and time resolved imaging. The 128×120 prototype has a pixel pitch of 7.83 μm making it the smallest pixel reported for SPAD image sensors. A low power, high density 40nm bottom tier hosts the quenching front end and processing electronics while an imaging specific 65nm top tier hosts the photo-detectors with a 1-to-1 hybrid bond… CONTINUE READING
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