Backlog Aware Scheduling for Large Buffered Crossbar Switches

Abstract

A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with input groups), distributes the switch fabric across multiple chips, which communicate via high speed interconnects enabled by proximity communication (PC), a recently developed… (More)
DOI: 10.1109/ICC.2008.19

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