Background ADC calibration in digital domain

@article{Tsang2008BackgroundAC,
  title={Background ADC calibration in digital domain},
  author={Cheongyuen W. Tsang and Yun Chiu and Johan P. Vanderhaegen and Sebastian Hoyos and Charles Chen and Robert W. Brodersen and Borivoje Nikolic},
  journal={2008 IEEE Custom Integrated Circuits Conference},
  year={2008},
  pages={301-304}
}
A 100 MS/s pipelined ADC is digitally calibrated by a slow SigmaDelta ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411 kHz sinusoidal input, the peak SNDR improves from 28 dB to 59 dB and the SFDR improves from 29 dB to 68 dB. The complete 0.13 mu ADC SoC occupies a die size of 3.7 mm times 4.7 mm, and consumes a total power of 448 mW. 
Highly Cited
This paper has 61 citations. REVIEW CITATIONS
27 Citations
14 References
Similar Papers

Citations

Publications citing this paper.
Showing 1-10 of 27 extracted citations

61 Citations

01020'10'12'14'16'18
Citations per Year
Semantic Scholar estimates that this publication has 61 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-10 of 14 references

B

  • C. Tsang, Y. Chiu
  • Nikolic, “A 1.2V, 10.8mW, 500kHz Sigma-Delta…
  • 2006
2 Excerpts

A 14 blinear capacitor selftrimming pipelined ADC

  • B. E. Boser
  • International Solid - State Circuits Conference
  • 2004

An adaptive filtering platform for digitally calibrated A/D conversion,

  • Y. Chiu
  • Berkeley Wireless Research Center (BWRC) retreat…
  • 2004
1 Excerpt

Similar Papers

Loading similar papers…