Backgate bias and stress level impact on giant piezoresistance effect in thin silicon films and nanowires

@article{Passi2010BackgateBA,
  title={Backgate bias and stress level impact on giant piezoresistance effect in thin silicon films and nanowires},
  author={Vikram Passi and Florent Ravaux and Emmanuel Dubois and Jean-Pierre Raskin},
  journal={2010 IEEE 23rd International Conference on Micro Electro Mechanical Systems (MEMS)},
  year={2010},
  pages={464-467}
}
Top-down fabrication and electrical characterization of undoped p-type silicon nanowires with and without stress using a 4-point bending fixture are shown. Uniaxial tensile stress values of around 200 MPa are possible with the bending fixture. Giant piezoresistance is measured for wires of 50 nm-thick and widths from 25 nm to 1 µm. Nonlinear characteristics at high stress level and impact of backgate bias on piezoresistance coefficient are presented for the first time.