BPS : A Bufferless Switching Technique for NoCs ∗

@inproceedings{Gmez2008BPSA,
  title={BPS : A Bufferless Switching Technique for NoCs ∗},
  author={Crisṕın G{\'o}mez and M. E. G{\'o}mez and Pedro Diego L{\'o}pez and Jos{\'e} Duato},
  year={2008}
}
Wires are an abundant resource in on-chip networks. This wiring capability has led to networks with very wide links, compared with the ones that we can find on off-chip networks. As an example of such systems, in [2, 8], two different NoCs are proposed with link widths of 80 and 256 bits, respectively. These wide links provide low latency communication between the nodes of the network because the packet is composed by a low number of flits. However, there are a high number of systems that can… CONTINUE READING

From This Paper

Figures, tables, and topics from this paper.

Citations

Publications citing this paper.
SHOWING 1-10 OF 12 CITATIONS

References

Publications referenced by this paper.
SHOWING 1-10 OF 11 REFERENCES

An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip

  • P. T. Wolkotte
  • Proc. of the 19th IEEE Int. Parallel and…
  • 2005
Highly Influential
4 Excerpts

Assessing the Impact of Flow Control and Switching Techniques on Switch Performance for Low Latency NoC Design

  • F. Martini, D. Bertozzi, L. Benini
  • the First Workshop on Interconnection Network…
  • 2007
2 Excerpts

Network on chips

  • G. De Michelli, L. Benini
  • Morgan Kaufmann
  • 2006
1 Excerpt

Route packets

  • W. J. Dally, B. Towles
  • not wires: on-chip inteconnection networks, Proc…
  • 2001
2 Excerpts

Similar Papers

Loading similar papers…