BIST design optimization for large-scale embedded memory cores

@article{Chien2009BISTDO,
  title={BIST design optimization for large-scale embedded memory cores},
  author={Tzuo-Fan Chien and Wen-Chi Chao and Chien-Mo James Li and Yao-Wen Chang and Kuan-Yu Liao and Ming-Tung Chang and Min-Hsiu Tsai and Chih-Mou Tseng},
  journal={2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers},
  year={2009},
  pages={197-200}
}
Built-in Self Test (BIST) is a crucial technique for testing embedded memory cores in a System-on-Chip (SoC). However, there is not much published work on BIST design optimization for multiple memory cores in the SoC designs. In this paper, we present a method for the BIST design optimization problem for large-scale SoC embedded memory cores, considering various real-world constraints such as peak current, IR drop, etc. Our method is based on a three-stage technique: (1) assignment, (2… CONTINUE READING