BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning

@article{Sadi2016BISTRMBR,
  title={BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning},
  author={Mehdi Sadi and Gustavo K. Contreras and Dat Tran and Jifeng Chen and LeRoy Winemberg and Mark Mohammad Tehranipoor},
  journal={2016 IEEE International Test Conference (ITC)},
  year={2016},
  pages={1-10}
}
In this paper, we present a novel methodology, BIST-RM, to accurately predict the degradation due to aging mechanisms in a SoC at run-time by utilizing the existing LBIST hardware and software implemented Machine Learning classifier. Using an innovative method, we convert ATPG-generated transition delay patterns into LBIST patterns, and the corresponding responses are utilized in developing the predictor. A gate-overlap and path delay-aware pattern selection algorithm selects the features for… CONTINUE READING

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Key Quantitative Results

  • We implemented our proposed flow on SoC benchmark circuits, and the results demonstrated worst-case prediction accuracy of 94% to 97%.

References

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