BEOL Advance Interconnect Technology Overview and Challenges

Abstract

An overview of the semiconductor roadmap of interconnects process transition from 0.13mum to 45nm using current proven state- of-the-art manufacturing technology in relation to the integration of dielectric material progressing from fluorinated silica glass to porous low-k will be discussed. Key challenges of process integration with shrinking dimension to meet the ever-demanding timing delay due to interconnects will be shown. Process enhancements with design for manufacturing concepts are addressed to meet the industrial specifications of reliability and chip package interaction for mass production.

Cite this paper

@article{Hsia2008BEOLAI, title={BEOL Advance Interconnect Technology Overview and Challenges}, author={Liang Choo Hsia and J. B. Tan and Bei Chao Zhang and Wu Ping Liu and Yeow Kheng Lim and Dong Kyun Sohn}, journal={2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)}, year={2008}, pages={28-29} }