BEAR: Techniques for mitigating bandwidth bloat in gigascale DRAM caches

@article{Chou2015BEARTF,
  title={BEAR: Techniques for mitigating bandwidth bloat in gigascale DRAM caches},
  author={Chia-Chen Chou and Aamer Jaleel and Moinuddin K. Qureshi},
  journal={2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA)},
  year={2015},
  pages={198-210}
}
Die stacking memory technology can enable gigascale DRAM caches that can operate at 4x-8x higher bandwidth than commodity DRAM. Such caches can improve system performance by servicing data at a faster rate when the requested data is found in the cache, potentially increasing the memory bandwidth of the system by 4x-8x. Unfortunately, a DRAM cache uses the… CONTINUE READING