Avoiding Timing Anomalies Using Code Transformations

@article{Kadlec2010AvoidingTA,
  title={Avoiding Timing Anomalies Using Code Transformations},
  author={Albrecht Kadlec and Raimund Kirner and Peter P. Puschner},
  journal={2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing},
  year={2010},
  pages={123-132}
}
Divide-and-conquer approaches to worst-case execution-time analysis (WCET analysis) pose a safety risk when applied to code for complex modern processors: Interferences between the hardware acceleration mechanisms of these processors lead to timing anomalies, i.e., a local timing change causes an either larger or inverse change of the global timing. This phenomenon may result in dangerous WCET underestimation. This paper presents intermediate results of our work on strategies for eliminating… CONTINUE READING