Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits

@inproceedings{Chou1998AverageCaseOT,
  title={Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits},
  author={Wei-Chun Chou and Peter A. Beerel and Ran Ginosar and Rakefet Kol and Chris J. Myers and Shai Rotem and Kenneth S. Stevens and Kenneth Y. Yun},
  booktitle={ASYNC},
  year={1998}
}
We describe an automated method (3D-map) for determining near-optimal decomposed generalized C-clement (gC) implementations of extended burst-mode asynchronous controllers. Average-case optimization is performed so that frequent paths are accelerated, possibly at the expense of less frequent paths. The overall effect, as quantified using Elmore delay analysis, is a circuit that has near-optimal performance for the average or common case. 
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Computing the area versus delay trade-off curves in technology mapping

IEEE Trans. on CAD of Integrated Circuits and Systems • 1995
View 4 Excerpts
Highly Influenced

Paver . AMULET 2 e : An asynchronous embedded controller

J. D. Garside S. B. Furber, S. Temple, J. Liu, P. Day, C. N.
1997

Design of a low-latency asyn- chronous adder using speculative completion

S. M. Nowick
IEE Proceedings, Part E, Computers and Digital Tech- niques, 143(5):301{307, September • 1996
View 1 Excerpt

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