Corpus ID: 9997925

Automation in Design for Test for Asynchronous Null Conventional Logic (NCL) Circuits

@inproceedings{Satagopan2005AutomationID,
  title={Automation in Design for Test for Asynchronous Null Conventional Logic (NCL) Circuits},
  author={Venkat Satagopan and Bonita Bhaskaran and Waleed K. Al-Assadi and Scott C. Smith},
  year={2005}
}
The semiconductor era has been thriving since the past four decades but as we continually attain smaller chip sizes comprising of millions of transistors, the problems grow at an unmitigated speed too. Testing such huge circuits poses a huge problem unless tackled prudently. The best case scenario given the current circumstances would be to create a favorable test environment on-chip by implementing Design for Test (DFT) techniques. Asynchronous digital design methodologies are currently… Expand

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