Automating the layout of reconfigurable subsystems via template reduction

Abstract

The focus of this work is the automatic generation of mask layouts, which is performed by the VLSI layouts, which is performed by the VLSI generator. This paper also presents method of automating the layout process, the template reduction method. The goal of the template reduction is not only the removal of unneeded routing resource, but also the removal of… (More)
DOI: 10.1007/978-3-540-30117-2_89

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