Automatic verification of Floating Point Units

  title={Automatic verification of Floating Point Units},
  author={Udo Krautz and Viresh Paruthi and Anand Arunagiri and Sujeet Kumar and Shweta Pujar and Tina Babinsky},
  journal={2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)},
Floating Point Units (FPUs) pose a singular challenge for traditional verification methods, such as coverage driven simulation, given the large and complex data paths and intricate control structures which renders those methods incomplete and error prone. Formal verification (FV) has been successfully leveraged to achieve the high level of quality desired of these critical logics. Typically, FV-based approaches to verify FPUs rely on introducing higher level abstractions to allow reasoning… CONTINUE READING