Automatic transistor and physical design of FPGA tiles from an architectural specification

@inproceedings{Padalia2003AutomaticTA,
  title={Automatic transistor and physical design of FPGA tiles from an architectural specification},
  author={Ketan Padalia and Ryan Fung and Mark Bourgeault and Aaron Egier and Jonathan Rose},
  booktitle={FPGA},
  year={2003}
}
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywhere from 50 to 200 man-years simply in the layout step. To date, automated tools have only been employed in small parts of the periphery and programming circuitry. The core tiles, which are repeated many times, are subject to painstaking manual design and layout. In this paper we present a new system (called GILES, for… CONTINUE READING

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MOSIS Scalable CMOS (SCMOS) Design Rules

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  • http://www.mosis.org/Technical/Designrules/scmos…
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