Automatic formal verification of fused-multiply-add FPUs

@article{Jacobi2005AutomaticFV,
  title={Automatic formal verification of fused-multiply-add FPUs},
  author={Christian Jacobi and Kai Weber and Viresh Paruthi and Jason Baumgartner},
  journal={Design, Automation and Test in Europe},
  year={2005},
  pages={1298-1303 Vol. 2}
}
In this paper we describe a fully-automated methodology for formal verification of fused-multiply-add floating point units (FPUs). Our methodology verifies an implementation FPU against a simple reference model derived from the processor's architectural specification, which may include all aspects of the IEEE specification including denormal operands and exceptions. Our strategy uses a combination of BDD- and SAT-based symbolic simulation. To make this verification task tractable, we use a… CONTINUE READING

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