Automatic Synthesis of Gated Clocksfor Power Reduction in Sequential

  • CircuitsL. Benini P. Siegel G. De MicheliCenter
  • Published 1994


With the proliferation of portable devices and increasing levels of chip integration, reducing power consumption is becoming of paramount importance. We describe a technique to automatically synthesize gated clocks for nite-state machines (FSMs) to reduce power in the nal implementation. This technique recognizes self-loops in the FSM (either from the state… (More)


  • Presentations referencing similar topics