Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms


We consider the problem of automatic mapping of computation-intensive loop nests onto FPGA hardware. The regular cell array structure of these chips reflects the parallelism in regular loop-like computations. Furthermore, the flexibility of FPGAs allows the cost-effective implementation of reconfigurable high performance processor arrays. So far, there… (More)
DOI: 10.1023/A:1024447517501


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@article{Bednara2003AutomaticSO, title={Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms}, author={Marcus Bednara and J{\"u}rgen Teich}, journal={The Journal of Supercomputing}, year={2003}, volume={26}, pages={149-165} }