Automatic Incorporation of On-Chip Testability Circuits

  title={Automatic Incorporation of On-Chip Testability Circuits},
  author={Noriyuki Ito},
This paper presents a system which automatically incorporates testability circuits into ECL chips. This system incorporates three types of circuit: (1) random access scan circuit, (2) clock suppression circuit for delay fault testing, and (3) pin scan-out circuit for chip I/O pin observation in board testing. Fanout destinations of each gate in the testability circuits are localized on a chip to keep the logical net length within the limit. This system was used to develop the new Fujitsu VP… CONTINUE READING


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